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 Contact Linear Technology for Potential Replacement
FOR INFORMATION PURPOSES ONLY
OBSOLETE:
LT1948 DC/DC Converter for TFT-LCD Panels
August 2000
Final Electrical Specifications
I I I I I I I I I I
Complete Solution Under 1.2mm Develops Three Outputs from a 3.3V or 5V Supply Externally Programmable VON Delay Fixed Frequency Low Noise Outputs All Ceramic Capacitors Operates at 3MHz Switching Frequency Fast Transient Response Few External Components Required 2.6V to 6V Input Range Tiny 8-Lead MSOP Package
APPLICATIO S
I I I I
TFT-LCD Notebook Display Panels TFT-LCD Desktop Monitor Display Panels Digital Cameras Handheld Computers
The LT(R)1948 is a highly integrated multiple output DC/DC converter designed for use in TFT-LCD panels. The device contains two independent switching regulators: the main regulator has an adjustable output voltage with an internal 1.1A switch that can generate a boosted voltage as high as 30V while the second regulator generates 23V at up to 10mA for positive bias. A simple level-shift charge pump off the main switch node generates the negative bias voltage. An external capacitor sets the delay time from AVDD reaching final value to 23V appearing at the VON pin. The 3MHz switching frequency allows the use of tiny low profile chip inductors and capacitors throughout, providing a low noise, low cost total solution with all components under 1.25mm in height. The device operates from an input range of 2.6V to 6V and is available in an 8-lead MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
D3A
BAT54S
L1, 2.2H VIN 2.5V TO 6V C1 2.2F L2, 2.2H L3 2.2H D2 CMDSH-3 C3 0.22F
VIN SW2 LT1948 VO2 CT C6 22nF
C1, C2: TAIYO YUDEN LMK212BJ225 C3: TAIYO YUDEN TMK316BJ224 C4: TAIYO YUDEN EMK212BJ224
C5: TAIYO YUDEN LMK212BJ105 L1-L3: TAIYO YUDEN LB2012-2R2
Figure 1. 3.3V Powered TFT-LCD Bias Generator
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
TYPICAL APPLICATIO
D3B C5 1F
VOFF -8V 15mA
C4 0.22F D1 MBRM120
SW1 FB1
R1 53.6k
AVDD 8V 260mA C2 2.2F VON 23V 10mA
VIN 5V/DIV VON 20V/DIV
R2 10k GND VON
AVDD 10V/DIV VOFF 10V/DIV 2ms/DIV
1948 TA01a
1948 F01
U
Start-Up Waveforms
FEATURES
DESCRIPTIO
U
1
LT1948
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW FB1 CT SW1 GND 1 2 3 4 8 7 6 5 VON VO2 SW2 VIN
VIN Voltage ................................................................ 8V CT Voltage.................................................................. 6V SW1, SW2 Voltage .................................................. 36V FB Voltage ................................................................. 3V VON, VO2 Voltage..................................................... 30V Operating Temperature Range (Note 2) .. - 40C to 85C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1948EMS8 MS8 PART MARKING LTNR
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 200C/W
Consult factory for Industrial and Military grade parts.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V unless otherwise specified.
SYMBOL Supply Current Reference Voltage Reference Line Reg CT Source Current CT Voltage to Turn On Q3 FB1 Voltage to Begin CT Charge SW1 Current Limit SW2 Current Limit SW1 Saturation Voltage SW2 Saturation Voltage Oscillator Frequency Maximum Duty Cycle 0C TA 85C -40C TA 0C VO2 Pin Resistance SW1, SW2 Error Amp Gain SW1, SW2 Error Amp Gm FB1 Regulation Voltage
q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS Not Switching 2.7V < VIN < 8V VFB1 = 1.3V
MIN
TYP 7 1.26 0.01
MAX 13
UNITS mA V %/V
4.5 1.25 1.17
5.5 1.28 1.20 1.5 0.8 350 250
6.5 1.30 1.23
(Note 3) (Note 3) ISW1 = 800mA ISW2 = 300mA
q
1.2 0.5
410 300 3.6 90
2.4 70 69 67
3.2 75
Measured to Ground
400 100 50 1.240 1.230 22 1.260 0.01 23 200 0.01 0.01 1.280 1.285 0.05 24 260 5 2
A/V V V V mV A A
FB1 Line Regulation VO2 Regulation Voltage VON Switch Drop SW1 Leakage Current SW2 Leakage Current
2.7V < VIN < 8V VO2 = 25V, 7mA Load from VON, CT Voltage >1.30V Switch Off, SW1 Voltage = 3.3V Switch Off, SW2 Voltage = 3.3V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1948 is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating
temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Current limit guaranteed by design and/or correlation to static test.
2
U
A V V A A mV mV MHz % % % k V/V
W
U
U
WW
W
LT1948
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect resistor divider tap here. Set AVDD according to AVDD = 1.26V(1 + R1/R2). CT (Pin 2): Timing Capacitor Pin. Connect a 22nF capacitor from CT to ground to program a 3ms delay from FB1 reaching 1.26V to VON turning on. SW1 (Pin 3): AVDD Switch Node. Connect inductor and D1 here (see Figure 1). Minimize trace area at this pin to keep EMI down. GND (Pin 4): Ground. Connect directly to local ground plane. VIN (Pin 5): Input Supply Pin. Must be bypassed with a ceramic capacitor close to the pin. SW2 (Pin 6): VO2 Switch Node. Connect inductor and D2 here. Minimize trace area at this pin to keep EMI down. VO2 (Pin 7): Sense Pin for 23V Output. Connect to VO2 output capacitor. This node is also internally connected to the emitter of Q3 (see Block Diagram), the high side switch between VO2 and VON. VON (Pin 8): This is the Delayed 23V Output. VON becomes 23V after the internal timer times out.
OPERATIO
To best understand operation of the LT1948, please refer to the LT1948 Block Diagram. The device contains two switching regulators, a timer and a high side switch. Three outputs can be generated: an adjustable AVDD output, a charge-pumped inversion of the AVDD output, called VOFF, and a 23V/15mA output, called VON. Q3 keeps VON off for an externally set time interval, set by a capacitor connected to the CT pin. The switching frequency of both switchers is 3MHz, set internally. The switchers are current mode and are internally compensated. The main AVDD switcher is current limited at 1.5A, while the second VON switcher is limited to 800mA. They share the same 1.26V reference voltage.
AVDD R1 1 R2 D1 3 C2 4 2
U
U
U
U
When the input voltage is below approximately 2.4V, an undervoltage lockout circuit disables switching. When AVDD is less than its final voltage, Q4 is turned on, holding the CT pin at ground. When AVDD reaches final value, Q4 lets go of the CT pin, allowing the 5.5A current source to charge the external capacitor, CT. When the voltage on the CT pin reaches 1.25V, Q3 turns on, connecting VO2 to VON. Capacitor value can be calculated using the following formula: C = (5.5A * tDELAY)/1.25V A 22nF capacitor results in approximately 3ms of delay.
VON 8 7 6 5 L1-L2 VIN C1 L3 D2 C3
GND C6 D3A D4B VOFF C4
1948 F02
Figure 2. Recommended Component Placement
3
LT1948
BLOCK DIAGRA W
VIN GND VIN FB1
- - + +
REF R
OSC S Q
SW1
Q1
+ +
0.01
SLOPE 1
8A 28mV
-+
CT Q4
REF
REF
1.26V REFERENCE AND UNDERVOLTAGE LOCKOUT
VON 3MHz OSCILLATOR Q3 REF VO2
OSC SLOPE 1 SLOPE 2
- - + +
REF R
OSC S Q
SW2
Q2
+ +
0.03
SLOPE 2
1948BD
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PART NUMBER LT1949 LT1317 LT1308B LT1615 LT1930 DESCRIPTION 600kHz, 1A Switch PWM DC/DC Converter 2-Cell Micropower DC/DC with Low-Battery Detect 600kHz Single Cell Step-Up Regulator Micropower Step-Up Regulator in SOT-23 1.2MHz, Step-Up Regulator in SOT-23 COMMENTS 10V at 175mA from 3.3V Input 3.3V at 200mA from 2-Cell Input 5V at 1A from a 1-Cell Li-Ion Battery 20V at 12mA from 2.5V Input, 5-Lead SOT-23 Package 5V at 480mA from 3.3V, 5-Lead SOT-23 Package
1948i LT/TP 0800 4K * PRINTED IN USA
4
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
(c) LINEAR TECHNOLOGY CORPORATION 2000


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